1. Field of the Invention
This invention relates to digital data communication circuits, and more particularly to the testing of serial data communication circuits.
2. Description of the Relevant Art
Electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). Simultaneous transmission of multiple signals is accommodated by several wires routed in parallel (i.e., buses). Most computer systems have a modular architecture centered around a bus which serves as a shared communication link between system components. The two major advantages of shared buses over direct communication links between system components are versatility and low cost. By defining a standard interconnection scheme for a given bus, new devices may be easily connected to the bus. The cost of the bus is low because it is shared among the number of components connected to the bus.
Due to technological advances, the signal processing capabilities of more modern electronic devices (e.g., microprocessors) are outstripping the signal transfer capabilities of conventional parallel buses. To their detriment, parallel buses have physical limitations which place an upper limit on the rate at which information can be transferred over the bus. For example, the electrical characteristics and loading of each wire of a bus may vary, causing signals transmitted simultaneously upon the bus to be received at different times. Bus timing must take into consideration worst case delays, resulting in reduced data transfer rates of systems employing parallel buses.
A serial data path, on the other hand, is a direct communication link between a single transmitter and a single receiver. Such a serial data path typically includes a dedicated transmission medium connected between the transmitter and receiver. The transmission medium may be, for example, a differentially-driven pair of wires or a fiber-optic cable. In cases where the transmission medium is a pair of wires, the communication link (i.e., channel) has a defined electrical loading and is typically optimized for minimum signal delay. As a result, the rate at which electrical signals can be transferred over such a serial data path exceeds the data transfer rate of a common shared parallel bus.
A typical serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data at an input port, converts the parallel data to a serial data stream in response to a transmit clock signal, and provides the serial data stream at an output port. The serial data stream includes data "windows" between data transition periods. The receiver receives a serial data stream at an input port, converts the serial data stream to parallel data, and provides the parallel data at an output port.
Serial data streams are typically self-clocking. That is to say the transmit clock signal used to transmit the data contains timing information necessary to extract the data from the serial data stream. Both the data and the timing information (i.e., the transmit clock signal) are discernible within the serial data stream. A given receiver typically recovers the transmit clock signal from the serial data stream and uses the transmit clock signal to recover the data. The receiver typically uses the recovered transmit clock signal to sample the serial data stream in the center of the data windows of the serial data stream (i.e., midway between the data transitions).
A variety of noise sources can cause the amount of time between data transitions of a serial data stream to fluctuate or "jitter". A practical receiver must be able to accurately extract the data from the serial data stream despite the presence of a certain amount of jitter in the input serial data stream. For this reason, receivers typically include phase-locked loop ("PLL") circuitry to recover transmit clock signals from serial data streams. The use of PLL circuitry provides some immunity to jitter in the serial data stream.
FIG. 1 is a block diagram of a typical PLL clock signal recovery/data sampling circuit 10 used within a serial data receiver. PLL clock signal recovery/data sampling circuit 10 includes a phase comparator 12, a loop filter 14, a voltage-controlled oscillator ("VCO") 16, a divide-by-n circuit 17, and an edge-triggered latch 18. Phase comparator 12 receives a frequency-divided Q.sub.1 ' signal produced by divide-by-n circuit 17 (i.e., a frequency-divided clock signal) and a serial data stream. Phase comparator 12 produces an a.c. error signal having a short term average value substantially proportional to the phase difference between the frequency-divided Q.sub.1 ' signal and the serial data stream. Loop filter 14 may be, for example, a low pass filter. Loop filter 14 receives the a.c. error signal and produces a low pass filtered error signal substantially proportional to the short term average value of the a.c. error signal. VCO 16 then produces the Q.sub.1 ' output signal and a complementary Q.sub.1 output signal. The frequencies of the Q.sub.1 ' and Q.sub.1 output signals are dependent upon the error signal and the number n, where n is an integer greater than or equal to 1 as described below. When n=1, the Q.sub.1 output signal of VCO 16 is the transmit clock signal recovered from the serial data stream. Divide-by-n circuit 17 receives the Q.sub.1 ' output signal and divides the frequency of the Q.sub.1 ' output signal by a number n, where n is an integer greater than or equal to 1, producing the frequency-divided Q.sub.1 ' signal. Edge-triggered latch 18 recovers the serial data from the serial data stream using the Q.sub.1 output signal. Edge-triggered latch 18 samples the serial data stream (at a data or "D" input) upon the rising edge of the Q.sub.1 output signal (at a clock signal or "C" input), producing sampled serial data at a Q.sub.2 output.
FIG. 2 is a timing diagram showing the temporal relationships between the serial data, Q.sub.1 ' and Q.sub.1 output signals, and the sampled serial data, for n=1. The serial data stream includes data "windows" separated by data transition periods. Parallel lines 20 represent jitter existing within the serial data stream. VCO 16 produces output signal Q.sub.1 ' having rising edges synchronized to data transitions within the serial data stream. Output signal Q.sub.1 is the complement of signal Q.sub.1 ', and has rising edges nominally midway between the data transitions of the serial data stream. Edge-triggered latch 18 produces the sampled serial data in response to the rising edges of signal Q.sub.1, thus edge-triggered latch 18 samples the serial data edges nominally midway between the data transitions. As sampling the serial data near one of the data transitions on either side of a data window may result in an error, this data sampling method minimizes the chance of an error occurring during data sampling.
Serial data transceivers offering, digital signal transmission rates exceeding 1 gigabit per second are now commercially available. The testing of such transceivers at their normal operating speeds, however, presents many technical challenges. Serial data transceiver test methods must verify that a given transmitter produces a serial data stream having less than or equal to a specified maximum amount of jitter. It would thus be beneficial to include testing elements within a serial data transceiver to facilitate measurement of an amount of jitter present within a serial data stream produced by a high-speed transmitter having an extremely short data window. Measuring jitter is important, especially in high speed applications, since knowledge gained from jitter testing can be used to direct a more appropriate sampling position within relatively short data windows.